1. FIELD OF INVENTION
The present invention relates to oscillator circuits for phase-locked loops with digital control of the frequency.
2. DESCRIPTION OF PRIOR ART
Numerically controlled oscillators used in phase-locked loops have in the past been provided with digital control words in order to attempt to duplicate the exact frequency and phase of a noise corrupted input signal. Examples are set forth in U.S. Pat. Nos. 3,422,374; 3,792,378; 3,818,345 and 4,053,879.
The numerically controlled oscillators provided output clock signals at nominal center frequencies plus or minus an amount determined by a digital control number or word applied as an input signal. The digital control word was accumulated in an accumulator until either positive or negative overflow occurred. The accumulator was then reset to zero and the oscillator output signal either delayed or advanced in a phase modulator by an amount of phase corresponding to a single cycle of the oscillator.
Several disadvantages occurred with these oscillators. There was not consistent correspondence between the number removed from the accumulator during reset and the fixed phase added to or subtracted from the oscillator frequency in the phase modulator, resulting in highly undesirable noise in the phase-locked loop. Also, the requirement of both advancing and delaying the phase considerably increased the complexity of circuitry required. Additionally, for output clock nominal frequencies in the range of several hundred kilohertz often used in space craft communication and elsewhere, a reference oscillator frequency in the order of approximately fifty megahertz was required, making digital logic operations quite difficult to perform.